1. Field of the Invention
The present invention relates to a microcomputer with built-in flash memory, and more particularly to restriction of excessive voltage applied to the memory with errors in write-disturb time when writing data to the flash memory, and to improvements in the data write device so that data loss due to this excessive voltage does not readily occur.
2. Description of the Related Art
Data loss when writing data to the flash memory is a problem in microcomputers with built-in flash memories. FIG. 7A is a partial circuit diagram of a flash memory in which a non-volatile memory cell M of MOS structure is disposed within a matrix, and each gate (control gate) of the plurality of memory cells in the row direction is connected in common to the same word line W, and each drain of the plurality of memory cells M in the column direction is connected in common to the same bit line B. Furthermore, two adjacent memory cells M in the column direction form a pair of memory cells in which each source is connected, and the plurality of pairs of memory cells in the row direction are connected in common to the same source line S.
In this flash memory 100, when data is written to the selected memory cell Ms enclosed within the chain line in the figure, the prescribed voltages are applied to the word line W and the bit line B connected to the selected memory cell Ms, for example, 2V is applied to the word line, and 0.5V is applied to the bit line, and furthermore, the prescribed voltage is applied to the source line S connected to the selected memory cell Ms, so that, for example, data can be written to the memory cell Ms by applying 8V.
FIG. 9 is a partial block circuit diagram of the microcomputer 1A including the data-write device permitting data to be written to the flash memory 100 in this microcomputer. The microcomputer 1A is comprised of a flash memory 100, a main oscillator circuit 120, a CPU 110, and a clock generator circuit 160. The main oscillator circuit 120 employs a crystal oscillator and the like as the oscillation source, and outputs a clock signal. The CPU 110 operates with the clock signal output from the main oscillator circuit 120. The write clock generator circuit 160 generates a write clock signal for writing data to the flash memory 100 with the CPU clock signal generated by the CPU 110. The main oscillator circuit 120 may be external, and the microcomputer user is able to connect an external main oscillator circuit 120 of the desired frequency to the microcomputer 1 so that the CPU 110 operates with a clock signal of the relevant oscillating frequency.
In this data-write device, the CPU 110 operates with the clock signal from the main oscillator circuit 120, and starts the microcomputer 1A. Furthermore, when writing data to the flash memory 100 after the microcomputer 1A is started, similarly, the CPU clock is generated and output by the CPU 110 based on the main oscillator circuit 120 clock signal, and the write clock signal for writing data with this CPU clock signal is generated by the write clock generator circuit 160. The generated write clock signal and the address and data signals are input to the flash memory 100, and data is written to the memory cell selected with the address signal.
FIG. 8 is a diagram showing the timing with which data is written to the flash memory 100 with the generated write clock signal. When the write flag is set, the prescribed voltage is applied to the word line of the memory cell to which selected data is to be written at the rising edge of the write clock signal, and, simultaneously, the prescribed voltage is applied to the source line of the memory cell, and the bit line of the memory cell is set to ON with the data. Thus, current flows from the source line to the bit line in the selected memory cell, and data is written to the memory cell. A plurality of bits of data are normally written to a plurality of memory cells with one write clock in this operation.
The write clock falls prior to selecting the next data, the next write clock rises after the next data is selected, and data is written to another memory cell. The period during which the write clock rises and data is written, and the next write clock then rises and the next data is written, is referred to in a narrow sense as the ‘write disturb time’. The time required for one data write cycle when a plurality of write operations with a plurality of write clocks after the write flag is set is assumed as one cycle, is referred to in the wider sense as the ‘write disturb time’.
However, when data is written to the selected memory cell Ms in the flash memory 100 shown in FIG. 7A, as shown for the memory cell pair formed from the selected memory cell Ms in FIG. 7B and the memory cell (referred to as the ‘adjacent memory cell’) Mn, the voltage applied to the selected memory cell Ms is also applied to the source line and bit line connected to the adjacent memory cell Mn. Thus, the afore-mentioned write-disturb time increases, and when the electric potential of the bit line B decreases with data write, even if the voltage on the word line W of the adjacent memory cell Mn, in other words, the gate voltage, is low, an excessive gate voltage is applied during the write-disturb time, and as a result, the memory cell Mn is set to the ON state, current flows to the adjacent memory cell Mn from the source line S to the bit line B as shown by the dashed line in the same figure, current escapes into the selected Ms via the adjacent memory cell Mn, and data is lost.
This problem of data loss is referred to in Japanese Unexamined Patent Publication No. 2002-183109 (Shinkawa) wherein a technology is proposed in which the load program is executed at high-speed, and overwrite time reduced, by changing to a high-speed CPU run clock supplied from an external source during on-board overwrite in a micro controller with built-in non-volatile memory. Use of a high-speed clock in this manner can reduce write-disturb time, and is effective in preventing data loss.
Shinkawa's technology is effective when a high-speed clock can be supplied from an external source as with on-board overwrite, however this requires an external writer able to output a high-speed clock, and data write with only the internal oscillator circuit of the microcomputer itself is difficult to achieve.
Furthermore, in order to prevent the afore-mentioned data loss, it is desirable that data write be completed before the adjacent memory cell enters the ON state, and that the write-disturb time for the flash memory is set to an appropriate time. Conversely, it is desirable that design is such that the various constants of the flash memory circuit are set to ensure that data loss does not occur even with the prescribed write-disturb time.
However, since the write clock signal in the conventional microcomputer shown in FIG. 9 is generated from a clock signal generated with the main oscillator circuit 120, the frequency of the write clock signal is controlled by the frequency of the main oscillator circuit 120. Thus, when the user connects a high-frequency main oscillator circuit to the microcomputer having the same flash memory, the data loss problem will occur rarely since the write-disturb time is short. However, in cases where a low-cost microcomputer is employed at the user's request, and a low-frequency main oscillator circuit is mounted and thus the microcomputer operates at a low frequency, the write clock signal is also of low-frequency, write-disturb time increases, and data loss readily occurs.
In relation to this problem, consideration of write-disturb time based on the frequency of the main oscillator circuit clock signal mounted in the microcomputer, and design of a flash memory in which data loss does not occur even at this write-disturb time is possible, however this requires design of a flash memory having a write-disturb time differing for each frequency of the main oscillator circuit, and it is difficult to implement a microcomputer having different operating speeds while using a standardized flash memory, and the microcomputer becomes expensive.